1. Technical Field
The present invention relates to a package of a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor package and a method of fabricating the same.
2. Background of the Related Art
As semiconductor devices have been miniaturized, packages with a size close to a chip size have been developed, such as a flip chip package and a chip size package. The chip size package generally has a lower reliability when compared with a conventional leadframe style package. In particular, since a stress is applied to a coupling section of the chip size package due to the thermal expansion coefficient difference between the package and a circuit board, the chip size package may be separated from the circuit board during manufacturing, testing, or operation.
Recently, a technique for applying an underfill material on a joint surface of a semiconductor chip including solder balls has been introduced in order to improve the reliability of the chip size package. The underfill material relieves a stress applied to the solder balls to prevent the solder balls from coming off the semiconductor chip when the chip size package is coupled to the circuit board or during a thermal cycling test.
FIG. 1 is a cross-sectional view illustrating a conventional chip size package and a method of coupling the chip size package to a circuit board.
Referring to FIG. 1, a chip size package 10 includes a plurality of solder balls 14 formed on a joint surface of a semiconductor chip 12. The solder balls 14 are used as I/O terminals of the semiconductor chip 12, and the solder balls 14 can be formed by various methods as is known in the art.
A part of the solder ball 14 is bonded to the semiconductor chip 12, and a curved portion adjacent to the bonding portion has a weak resistance to stress. In order to relieve stress applied to the solder balls 14 and fix the solder balls 14 to the semiconductor chip 12, an underfill material 16 is applied on the bonding surface of the semiconductor chip 12. The underfill material 16 is applied between the solder balls 14, and then contacts curved surfaces of the solder balls 14 by curing and reflow processes.
Generally, the chip size package 10 is directly coupled to a circuit board 50 such as a printed circuit board (PCB). As illustrated, a solder mask 54 is formed on a coupling surface of the circuit board 50 to provide a region for coupling of the solder balls 14. The solder mask 54 includes a plurality of openings 58 corresponding to the solder balls 14 to prevent the solder balls 14 from melting and contacting other portions of the circuit board 50 in addition to the pads 56. The solder balls 14 are coupled to the pads 56 formed inside the openings in the circuit board 50.
FIG. 2 is a cross-sectional view illustrating a conventional chip size package coupled to a circuit board.
Referring to FIG. 2, as the soldering process is performed at a predetermined temperature, the solder balls 14 are coupled to the corresponding pads 56, respectively. When the chip size package 10 is heated to a reflow temperature of the solder balls 14 or higher, it is electrically and mechanically coupled to the circuit board 50. Here, the underfill material 16 is reflowed and pushed into the openings 58.
As illustrated in FIG. 2, in the conventional chip size package, the underfill material 16 is coupled to the solder mask 54 to form a stress relief layer, and is cured through an additional heating cycle to improve bonding strength. The underfill material 16 relieves stress applied to the solder balls 14 to prevent the solder balls 14 from coming off the circuit board 50 due to the thermal expansion coefficient difference during the heating cycle.
However, the underfill material of the conventional chip size package has fluidity, and may be reflowed or deformed during the repeated heating cycles. Therefore, the thermal expansion coefficient difference may lead to decreases in the stress relieving effect on the solder balls.
Also, since the semiconductor chip is small and thin, stress and cracks due to an external impact are quickly transmitted. Therefore, the chip size package may be separated from the circuit board in an edge portion that is the weakest portion of the semiconductor chip.
The present invention addresses these and other disadvantages of the conventional art.